The present invention relates to an input/output processing system of a plurality of virtual computers in a virtual computer system.
The fundamental function of an OS is to efficiently and advantageously utilize hardware resources such as CPU, main storage, secondary memory and input/output devices. Therefore, the OS multiplexes hardware resources and produces a required number of virtual resources in a virtual manner, thereby allowing respective users to use a computer as if they had their own hardware resources such as a plurality of CPUs. The multiplexing method comprises a time sharing method, namely, a method of assigning resources to divided times, and a space sharing method, namely, a method of assigning resources to divided areas. The hardware resources are multiplexed to be reformed in a usable state and to correspond to the virtual resources.
Such a virtual computer system should provide the same functions and environment as a real computer. Thus, it should prevent a user from recognizing that the computer is running under the guest environment and provide a guest environment for coupling a plurality of virtual computers (herein called guests) including a plurality of CPUs.
This is also applied to the input and output processes.
Generally speaking, in a virtual computer system, a real input and output apparatus structure recognized by a virtual computer monitor (called a host) for performing a management of resources has a different structure from that of the virtual input and output apparatus to be recognized by the guest.
To enable a plurality of guests to run concurrently on the real computer, only a portion of a physical input and output apparatus structure (guest subchannel) is shown to the guest. Furthermore, a virtual identification (B) of the input and output apparatus resources (virtual subchannel number) is different from a physical identification (C) (subchannel number) in the physical input and output apparatus structure.
To prevent the guest from recognizing this difference, all the input and output instructions it issues are obtained in the prior art virtual computer system by the host and the virtual identification (B) (guest subchannel number) of the above input and output apparatus resources constituting the input and output instruction operand is translated to a physical identification (C) (subchannel number) in a structure of a physical input and output apparatus. Then the input and output environment is ensured by the guest by enabling the host to issue the input and output instruction. Namely, even if the physical input and output apparatus is busy, it is seen by the guest as if the guest were using the input and output apparatus. This is also applied to a function of the input and output process.
An object of a virtual computer is to enable softwares of a different architecture to run on a single hardware (real computer). As the control information is co-owned by several guests, the input and output process, which includes an asynchronizing operation, cannot absorb the differences in the architecture on the hardware side. Thus, a host with control information corresponding to respective guests performs an emulation, thereby absorbing the difference.
In the prior art virtual computer system, all the input and output processes in a guest are normally obtained by a host. This naturally decreases its capability. This deterioration may exceed 20 percent. Further, in the prior art virtual computer system, the control information (subchannel information) within a hardware does not correspond with the guest. Thus, it is necessary for the host to always judge to which guest the input and output event occurring in a certain hardware source should be reported, causing the control logic for the input and output apparatus of the host to be complicated and thus increasing the host's overhead.
Therefore, it is necessary to provide an input and output control system which can increase the capability of a virtual computer system by minimizing host overhead.
FIGS. 1A and 1B show an input and output processing system in a conventional virtual computer system. FIG. 1A shows a model of the functional assignment in the conventional virtual computer system and FIG. 1B shows an example of the structure. In FIG. 1A, guests 101 and 102 are provided to host 103.
In the conventional virtual computer system, all the input and output processes are conducted through host 103 and the guest input and output instruction for virtual subchannels (VSCH) 041 and 042 corresponding to the processing object viewed from guests 101 and 102 can be replaced by the input and output instruction having physical subchannel (SCH) 020 as its object through an operand translation.
What is reported by using the above physical subchannel (SCH) 020 upon issuing the guest input/output interruption is reflected on the virtual subchannels (VSCH) 041 and 042 by host 103 and reported to individual guests 101 and 102.
Virtual subchannels (VSCH) 041 and 042 within host 103 provide control information for achieving an input and output environment from the viewpoint of respective guests 101 and 102. In the conventional system, this control information exists within host 103 and the content reported by the hardware 1041 (for example, provided within memory control apparatus (MCU) 202) through physical subchannel (SCH) 020 is interpreted by host 103 to be reflected on guest 101 or 102.
The physical subchannel (SCH) 020 is an actual subchannel which hardware 1041 has inside thereof. Even if the physical input/output apparatus (IOD) 105 has a plurality of physical input/output addresses, only one physical subchannel (SCH) 020 is obtained in correspondence with one physical input/output apparatus (IOD) 105 in the prior art.
The above explains the functional assignment in an input/output process in the prior art virtual computer system. This process will be explained in detail by referring to FIG. 1B.
At first, the structure of the conventional virtual computer system is explained.
Guest A 101, guest B 102 and the host are arranged in main storage unit (MSU) 203 on the real computer, as shown in FIG. 1B. The virtual subchannels (called VSCH hereinafter) 041 and 042 in host 103 is a virtual subchannel corresponding to the above individual guests A and B 101 and 102. It does not recite a state of the actual input/output apparatus but the input/output apparatus viewed from guests 101 and 102. Upon an interruption of an input/output operation to the guest, the guest subchannel number (virtual identification (B)) for reporting the interruption to individual guests 101 and 102 is also recited therein.
The guest subchannel translation tables (hereinafter called GST) 214 and 215 are for performing a translation between said guest subchannel number (a virtual identification (B)) and the physical subchannel number (physical identification (C)). The host uses the table when the guest input and output instruction is issued, enabling the guest subchannel number to be translated to a physical subchannel number.
Virtual address translation table 216 (hereinafter called VATT) within host 103 is for obtaining VSCH 212 or 213 based on the subchannel number of physical subchannel 020 transmitted from hardware 1041 and the information designating which path is used among paths connected to the device when an input/output interruption is initiated for input/output apparatus (IOD) 105.
Address translation table (ATT) 207 is provided in input/output processor (IOP) 206. It is an indexing structure for translating the physical input/output address, namely, the input/output apparatus address including the data transmission (communication) path to the subchannel number, and is usually formed by a high speed memory provided within input/output processor (IOP) 206. In the example shown in FIG. 1B, the translation structure operates to point to the same value, namely, subchannel (SCH) 020, regardless of whether or not input/output apparatus (IOD) 105 communicates with the body apparatus side by using either of channels (CHE) 208 or 209.
In a virtual computer system constructed as above, the operation of an input/output process event is explained as follows.
(a) Upon the guest input and ouput instruction execution:
(1) Guest input/output instructions are obtained by host 103 by a program corresponding to the guest executed by central processing unit (CPU) 201.
Host 103 converts an operand of the guest input/output instruction to the GST (for example 214) corresponding to guest 101 or 102, to obtain the corresponding physical subchannel number (physical identification (C)).
(2) Host 103 checks whether or not subchannel (SCH) 020 corresponding to the physical subchannel number obtained in the above is used by an input/output process by other guests. Namely, it is necessary for host 103 to manage the state of all the subchannels (SCH) 020.
(3) Where the in-use condition does not exist as a result of the check, host 103 issues an input/output instruction to subchannel (SCH) 020.
Then, instruction data is added, which designates that only the input/output path assigned to corresponding guest 101 or 102 can be used. For example, the path which can presently be used for the input/output process comprises only a path of channel (CHE) 208, input/output control appartus (IOC) 210, input/output apparatus (IOD) 105.
(b) Upon a guest input and output interruption:
(1) Hardware 1041 obtains subchannel (SCH) 020 corresponding to input/output apparatus (IOD) 105 and reports the condition of the input/output interruption by using ATT 207. By using this subchannel (SCH) 020, it interrupts host 103 together with the data representing a path in which the input/output interruption condition is produced, for example, the data designating channel (CHE) 208, input/output control apparatus (IOC) 210, and input/output apparatus (IOD) 105.
(2) Host 103 selects a virtual subchannel (VSCH) 041 based on the physical subchannel number of subchannels (SCH) 020 and which path is used, by using VATT 216. The interruption report is performed for guests 101 and 102 after the input and output interruption condition is recited in VSCH 041.
As recited above, in the conventional system, it is necessary for all the guest input/output processes to be performed by host 103 regardless of whether they are input/output instructions or input and output interruptions. Therefore, there is a problem that the overhead of host 103 is increased.
In the existing virtual computer system, the host provides a virtual interruption mask and an interruption queue for every logical CPU and a hardware interruption mask is made to correspond in a time divisional manner to the virtual interruption mask. Therefore, the interruption condition from the input/output apparatus is distributed to respective logical CPUs.
The above prior art system will be further explained by referring to the drawings.
FIG. 2 shows the general structure of the input/ output interruption of the prior art virtual computer system. It comprises a host 301, guests 302 and 303, hardware 304, logical CPUs 321, 322, 331 and 332, virtual interruption mask 421, 422, 431 and 432, hardware interruption masks 340 and subchannel 305.
Respective virtual interruption masks 421, 422, 431 and 432 are provided for logical CPUs 321, 322, 331 and 332 of guests 302 and 303. The content of the hardware interruption mask 340 is made to correspond to these respective virtual interruption masks in a time divisional manner, thereby enabling the interruption condition from the input/output apparatus to be recognized by respective logical CPUs.
These controls are conducted by the host. Namely, the conventional virtual computer system requires that all the input/output interruptions be distributed by the host. A host makes hardware interruption mask 340 is made to correspond, in a time divisional manner, to virtual interruption masks 421 to 432, which are viewed from the respective logical CPUs of the guest and distributes the input/output interruption for respective logical CPUs.
FIG. 3 shows the interruption control of the virtual computer system. The same portions as in FIG. 2 are designated by the same reference numbers. Virtual interruption masks 411, 421 and 422 are provided to respective logical CPUs and respective bits are made to correspond to the interruption request from different input/output apparatuses. Therefore, the interruption from the input/output apparatus is received only when the value of a bit is "1".
Respective mask bits of hardware interruption mask 340 correspond to interruption requests from different input/output apparatuses and the bit position is made to correspond to the respective virtual interruption masks on a one-to-one basis. The bit pattern of the mask is the same as the bit pattern of the virtual interruption mask corresponding to the logical CPU which is running on the current physical CPUs, and input/output interruption is received only when the bit value is "1".
The interruption report destination 350 describes the report destination CPU of the input/output interruption. The logical CPU which initiates the subchannel is selected as the destination report logical CPU.
The operations upon setting of the virtual interruption mask and/or upon the generation of the guest input/output interruption will be explained.
(a) Upon setting of the virtual interruption mask:
(1) The guest logical CPU-c designated by the reference number 321 determines the virtual interruption mask 421 as necessary. By making the value of the bit (for example i01) corresponding to the input/output apparatus "1", the interruption request from the subchannel 305 corresponding to the input/output apparatus can be received. The interruption report destination C in the subchannel is described.
(2) The host 301 reflects the most recent virtual interruption masks 411 to 422 on hardware interruption mask 340 in a time divisional manner to prepare for the input/output interruption.
(3) When a certain guest logic CPU (for example 322) is dispatched to a different physical CPU, the virtual interruption mask 422 corresponding to the guest logical CPU is reflected on the hardware interruption mask by a host which runs on a different physical CPU.
(b) Upon the issuance of the guest input/output interruption:
(1) When the interruption condition is produced by the input/output apparatus and the corresponding bit (for example i01) of the hardware interruption mask 340 is "1", the input/output interruption condition is reported to the host.
(2) The bit value alone (content of the respective i01) of the virtual interruption masks of 411 to 422 cannot determine which logical CPU should receive the report of the input/output interruption. The host determines the report destination C based on the interruption report destination 350 in the subchannel 305 corresponding to the input/output apparatus, which produces the input/output interruption, and reports the input/output interruption condition to the logical CPU-c.
In the prior art virtual computer system, all the correspondence between the virtual interruption mask and the hardware interruption mask is managed by the host and the input/output interruption is distributed in accordance with the report destination.
Therefore, the overhead increases and the host's load also increases, affecting the processing capability of the system.
In order to decrease the host's, the hardware interruption mask is made to correspond to respective logical CPUs. However, this results in an increase in the hardware amount, making the system less economical.